NVIDIA Expands CUDA-X Libraries to Power AI-Defined Semiconductor Fabs

NVIDIA introduced the cuPotential library and expanded its CUDA-X portfolio at SEMICON West 2026, providing semiconductor manufacturers with GPU-accelerated tools to construct AI-defined fabs. The updated libraries, deployed in partnership with Lam Research, KLA, Synopsys, and Cadence, enable engineers to simulate atomic interactions and process 3D inspection data at significantly higher speeds, addressing the growing complexity of advanced chip manufacturing.

How NVIDIA cuPotential Accelerates Atomic-Scale Chip Simulation

Understanding atomic and molecular interactions is a foundational requirement for modeling semiconductor materials, but these calculations traditionally demand immense computational time. NVIDIA cuPotential addresses this bottleneck by providing specialized GPU-accelerated functions that developers can integrate into existing software to model electrical forces across large numbers of atoms.

By making these modeling capabilities available to AI agents, the library allows autonomous systems to run, evaluate, and iterate on advanced molecular simulations. In early-access testing, cuPotential “accelerated already GPU-optimized workflows by an additional 2-3x”. Synopsys is among the early adopters utilizing cuPotential to accelerate its materials simulations.

The strategic intent behind these tools is to shift fab operations from manual engineering adjustments to autonomous, physics-based AI models.

"The semiconductor industry made the AI revolution possible. Now, AI is transforming how chips are built," said Tim Costa, vice president and general manager of industrial and computational engineering at NVIDIA. "As fabs race to meet demand for advanced chips, NVIDIA CUDA-X and Omniverse libraries give AI agents accelerated simulation and inspection tools to help engineers manage complexity, improve yield and advance AI-defined fabs."

What Speed Improvements Lam Research and KLA Achieve in AI-Defined Fabs

Beyond atomic simulation, AI-defined fabs require rapid processing of 3D data and high-resolution images to maintain production yields. NVIDIA expanded its accelerated computing stack to include NanoVDB, an open-source library for 3D data, and NVIDIA NPP, a library for GPU-based image processing. These tools directly target the physical inspection and etching processes on the fab floor.

Lam Research utilized NanoVDB to achieve a 30x faster wafer-etch simulation, Futurum Group reported. Simultaneously, KLA leveraged NPP to accelerate its defect detection capabilities, recording a 50x inspection kernel speedup.

To provide clarity on how these acceleration metrics apply across the broader semiconductor ecosystem, the following table synthesizes the reported performance gains across NVIDIA’s partner network:

These figures represent distinct workload accelerations rather than a cumulative total, highlighting performance gains across the entire chip development lifecycle from initial design to physical inspection.

How Synopsys and Cadence Apply Agentic AI to Chip Design

The integration of accelerated computing extends deeply into the Electronic Design Automation (EDA) phase. Synopsys is utilizing cuPotential, cuEST, and cuDSS to accelerate semiconductor simulations. Early QuantumATK results indicate a potential 30x speedup using cuEST, while S-Device benchmarks show a 12x speedup using cuDSS. Furthermore, Synopsys AgentEngineer solutions now interoperate with NVIDIA Nemotron open models and NVIDIA NeMo to support AI agents for chip design and verification.

Cadence is applying similar agentic AI frameworks to the design and simulation of electromechanical systems. The company’s AuraStack AI Super Agent optimizes advanced packages for heat and stress 8x faster using cuDSS with Cadence Celsius.

This push toward agentic design aligns with NVIDIA’s internal methodology. NVIDIA applies AI at five stages of chip design: laying out components, designing arithmetic circuits, general engineering assistance, verifying finished designs, and exploring novel layouts, The Batch reported. NVIDIA chief scientist Bill Dally noted that the company’s long-term vision includes engineers who dream of telling an AI model to design a new GPU, then skiing for a couple days while the system does the job. Systems like NVCell are already being used to automate the redesign of thousands of small reusable layout blocks required for new manufacturing nodes.

Why the Semiconductor Industry is Shifting to AI-Defined Fabs Now

The transition to AI-defined fabs is driven by the physical limits of traditional engineering workflows. As semiconductor manufacturing processes shrink to fit more components per area of silicon, the complexity of modeling materials behavior and manufacturing processes increases exponentially. Engineers must test process changes in digital twins before applying them in production, a task that requires massive parallel processing.

This shift is the latest evolution of a computing paradigm that began nearly two decades ago. CUDA was introduced by NVIDIA in 2007 to allow software developers to use GPUs for general-purpose processing, according to Supermicro. This foundational shift from purely graphical rendering to parallel computing laid the necessary groundwork for today’s high-performance computing demands.

The timing of the AI-defined fab framework—which spans AI physics, AI agents, and physical AI—reflects the industry’s urgent need to manage this exponential complexity. By integrating AI physics models directly into process development and fab operations, manufacturers can predict process behavior and improve yield without proportionally increasing construction time and operational costs.

The deployment of cuPotential and the expanded CUDA-X libraries marks a definitive shift in semiconductor manufacturing. The industry is moving from human-directed optimization to autonomous, physics-based AI agents capable of managing the atomic-level details of chip production at scale.